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The core board houses, amongst other things, a Microchip PIC18F97J60 microcontroller, a 10Base-T ethernet port and a 1024 Kilobit EEPROM. The primary means of expansion is via the four Serial Peripheral Interface (SPI) bus headers, each with a corresponding 8 bit digital IO or digital IO/ADC header. In addition to this, other headers are provided for easily connecting push-buttons, USART peripherals, and other Lettuce boards or I2C peripherals via an SPI master/I2C connector.

Core board overview

Some pictures of the core board in various stages of production:

Both sides of the circuit board

Circuit board showing holes

Closeup after soldering the PIC

Finished soldering the first board

Description [size] Format
Circuit schematic [32.1KB] Adobe Acrobat PDF
PCB layout [259.8KB] Adobe Acrobat PDF

PIC18F97J60 Microcontroller

The Lettuce-v1 core board is based around the Microchip PIC18F97J60 microcontroller. Its main features are:

The fact that very few external components are required to use most of these makes this microcontroller a particularly good choice for our purpose. The design of the core board aims to expose as many of these features as possible to allow for maximum functionality without the need for add-on components.

The core board runs at a voltage of 3.3v, and includes an onboard regulator and associated circuitry. The PIC18F97J60 clock is generated from a 25MHz crystal using the on-chip PLL module. This allows the clock frequency to be adjusted in software, up to a maximum of 41.67MHz.

1024 Kbit EEPROM

The core board includes a Microchip 25LC1024 1024 Kbit serial EEPROM, which is connected to the board's SPI slave bus. This can be accessed at speeds of upto 20MHz.

RJ45 Ethernet socket

This allows the core board to be plugged into an Ethernet network, to communicate with other Lettuce boards, computers, or any other devices using TCP/IP. This uses the PIC18F97J60s onboard Ethernet module, which supports full-duplex 10Base-T Ethernet (10 Mbits/s).

SPI Slave headers

The core board has four Serial Peripheral Interface (SPI) slave headers, allowing upto four individually-addressable SPI slave plugin devices to to be used. These can either be attached directly via a 90 degree 0.1-inch PCB socket (if the board is small enough), or via a short length of ribbon cable.

Each SPI slave header is buffered to allow greater isolation between connected devices, which may be running at high bus speeds. Each port has a seperate interupt channel, which allows the slave device to signal the CPU if required.

Each SPI slave connector is implemented as follows:

Pin Name Purpose
1 SDO Serial data from the CPU
2 SDI Serial data to the CPU
3 SCK Serial clock (generated by the CPU)
4 INT By strobing this high, the plugin can interrupt the CPU to indicate some condition (e.g. that it requires attention).
5 !SE This is normally high and is sent low by the CPU to indicate that the plugin is being addressed. Most plugins consist of a single SPI addressable IC, to which this can be connected to !CS (inverse chip select). Note: Only one plugin can be addressed at any one time.
6 SID This should be connected to !SE via a resistor. The value of the resistor is used to uniquely identify the plugin board (so each type of plugin board should use a different value resistor here)
7 Vdd +3.3v supply
8 Gnd Ground

Analog/Digital port headers

The core board has two 8-pin analog/digital port headers. The first six pins of these can be selected to be either analog inputs or digital inputs/outputs, the remaining two pins being fixed digital inputs/outputs.

The analog/digital port connector is implemented as follows:

Pin Name Purpose
1 AD0 Analog input/Digital input/output bit 0
2 AD1 Analog input/Digital input/output bit 1
3 AD2 Analog input/Digital input/output bit 2
4 AD3 Analog input/Digital input/output bit 3
5 AD4 Analog input/Digital input/output bit 4
6 AD5 Analog input/Digital input/output bit 5
7 D6 Digital input/output bit 0
8 D7 Digital input/output bit 1

Digital port headers

The core board has two 8-bit digital input/output port headers, which correspond directly to ports E and J on the PIC18F97J60.

The digital port connector is implemented as follows:

Pin Name Purpose
1 D0 Digital input/output bit 0
2 D1 Digital input/output bit 1
3 D2 Digital input/output bit 2
4 D3 Digital input/output bit 3
5 D4 Digital input/output bit 4
6 D5 Digital input/output bit 5
7 D6 Digital input/output bit 6
8 D7 Digital input/output bit 7

SPI Master header

This can be connected to an SPI master device, or even an SPI slave header on another Lettuce-v1 board, allowing boards to be daisy-chained. If this is connected then this device will itself become an SPI slave.

The SPI master connector is implemented as follows:

Pin Name Purpose
1 SDI Serial data to the CPU
2 SDO Serial data from the CPU
3 SCK Serial clock (generated by the external device)
4 INT By strobing this high, we can interrupt the master device to indicate some condition (e.g. that we require attention).
5 !SE This is normally high and is sent low by the master device to indicate that we are being addressed.
6 SID This is connected to !SE via a resistor to identify this board as Lettuce-v1-core.
7 Vdd +3.3v supply
8 Gnd Ground

Note that the SDI and SDO lines are reversed compared to the SPI slave connector, allowing a straight-through cable to be used to connect these together.

USART header

Dual Inverse-TTL USART header, for connecting directly to peripherals that work at these levels (e.g. LCD display modules), or to an RS-232, RS-485 or LIN connecton via a plugin converter board.

The USART connector is implemented as follows:

Pin Name Purpose
1 TX1 USART channel 1 transmit
2 TX2 USART channel 2 transmit
3 RX1 USART channel 1 receive
4 RX2 USART channel 2 receive
5 Gnd Ground
6 Gnd Ground
7 Vdd +3.3v supply
8 Vdd +3.3v supply

Buttons header

An array of 2-pin headers to which up to 6 push-buttons can be connected (pull-up resistors are included on the board).

Aux header

The Aux port is used to expose 'miscellaneous' features, including additional ADC inputs, timer interrupts and Pulse Width Modulation (PWM) outputs.

The AUX connector is implemented as follows:

Pin Name Purpose
1 RA3 Spare analog input
2 RA4 Digital IO/Timer0 external clock input
3 RC1 Digital IO/PWM output
4 RC0 Digital IO/Timer1/3 clock input
5 RC2 Digital IO/PWM output
6 RB5 Digital IO/Interupt on change
7 Vdd +3.3v supply
8 Gnd Ground

Reset header

Allows a reset switch to be added to reset the CPU if required.

ICSP header

Allows the PIC18F97J60 to be reprogrammed using a suitable In-Circuit Serial Programming device.

The ICSP connector is implemented as follows:

Pin Name Purpose
1 !MCLR Reset/programming voltage from programmer
2 Vdd Power supply from programmer
3 Gnd Ground
4 PGD Data to/from programmer
5 PGC Clock from programmer
6 NC Not connected

Note: This connector is designed to work with various Microchip PIC programmers, e.g. PicKit 2.

Component list

Below is a full list of components required to build the core board.


ID Value Package Description
U1 PIC18F97J60 LQFP100 Microcontroller
U2 LF33ABV TO220 +3.3v LDO voltage regulator
U3 74x3125 SO14 Quad 3-state buffer/bus switch
U4 74x3125 SO14 Quad 3-state buffer/bus switch
U5 74x3125 SO14 Quad 3-state buffer/bus switch
U6 74x3125 SO14 Quad 3-state buffer/bus switch
U7 25LC1024 SO8M 1024 Kbit SPI EEPROM


ID Type Description
S1 1x2 100mil header Reset switch connector
J1 1x6 100mil header ICSP (In circuit serial programming)
J2 RJ45 MagJack* 10Base-T Ethernet
J3 1x2 100mil header Power input
J4 2x4 100mil header AUX (Auxillary)
J5 2x4 100mil header USART (Serial ports)
J6 2x6 100mil header BTNS (Button inputs)
J7 2x4 100mil header SPI-M (SPI master port)
J8 2x4 100mil header SPI-1 (SPI slave port 1)
J9 2x4 100mil header AD1 (Analog/digital port 1)
J10 2x4 100mil header SPI-2 (SPI slave port 2)
J11 2x4 100mil header AD2 (Analog/digital port 2)
J12 2x4 100mil header SPI-3 (SPI slave port 3)
J13 2x4 100mil header DIG1 (Digital port 1)
J14 2x4 100mil header SPI-4 (SPI slave port 4)
J15 2x4 100mil header DIG2 (Digital port 2)

* = Bel-Stewart MagJack RJ45 connector, or equivalent, with integral ethernet magnetics and indicator LEDs.


ID Value Package Description
R1 4K7 0805 SPI-M ID
R2 1R 1W Input power limiter
R3 470R 0805 Power LED limiter
R4 470R 0805 Ethernet LED 1 limiter
R5 470R 0805 Ethernet LED 2 limiter
R6 2K26 0805 Ethernet RBIAS
R7 49R9 0805 Ethernet TX
R8 49R9 0805 Ethernet TX
R9 49R9 0805 Ethernet RX
R10 49R9 0805 Ethernet RX
R11 4K7 0805 SPI ID pull-up
R12 470R 0805 Button pull-down
R13 470R 0805 Button pull-down
R14 470R 0805 Button pull-down
R15 470R 0805 Button pull-down
R16 470R 0805 Button pull-down
R17 470R 0805 Button pull-down
R18 1M 0805 Across xtal
R19 100R 0805 ICSP MCLR isolation
R20 1K 0805 Reset sw pull-down
R21 4K7 0805 Reset sw pull-up
R22 0R 0805 ICSP PGD isolation (if reqd)
R23 0R 0805 ICSP PGC isolation (if reqd)
R24 10K 0805 Button pull-ups
R25 10K 0805 Button pull-ups
R26 10K 0805 Button pull-ups
R27 10K 0805 Button pull-ups
R28 10K 0805 Button pull-ups
R29 10K 0805 Button pull-ups
R30 10R 0805 SPI-M power isolation (if reqd)


ID Value Package Description
C1 22pF 0805 Oscillator
C2 22pF 0805 Oscillator
C3 100nF 0805 Supply decoupling
C4 100nF 0805 Supply decoupling
C5 100nF 0805 Supply decoupling
C6 100nF 0805 Supply decoupling
C7 100nF 0805 Supply decoupling
C8 100nF 0805 Supply decoupling
C9 100nF 0805 Ethernet
C10 100nF 0805 Ethernet
C11 100nF 0805 Supply decoupling
C12 100nF 0805 Supply decoupling
C13 100nF 0805 Supply decoupling
C14 100nF 0805 Power input filter
C15 220uF 200mil radial Power input filter
C16 100nF 0805 Power reg output filter
C17 25uF 100mil radial Power reg output filter
C18 10uF 100mil radial On-chip reg VCAP
C19 100nF 0805 Reset circuit


ID Value Package Description
L1 not critical 1206 Ethernet interface ferrite bead
X1 25MHz HC-49* Oscillator crystal
D1 1N4001A 300mil axial Power input rectifier
D2 Red LED 3mm dia Power on indicator
D3 1N4148 300mil axial SPI ID
D4 1N4148 300mil axial SPI ID
D5 1N4148 300mil axial SPI ID
D6 1N4148 300mil axial SPI ID

* = U4 or any other 200mil pitch crystal type also suitable.

Connections by PIC18F97J60 port

Port A

Bit Purpose/Connection
0 Eth LED A (link)
1 Eth LED B (activity)
2 AN2 - SPI plugin ID
3 AN3 - [AUX:0] (temp sensor)
4 TIMER0 - [AUX:1]
5 AN4 - [AD1:A1]

Port B

Bit Purpose/Connection
0 INT0 - [SPI1:INT]
1 INT1 - [SPI2:INT]
2 INT2 - [SPI3:INT]
3 INT3 - [SPI4:INT]
4 INT on change - [SPIM:INT]
5 INT on change - [AUX:5]

Port C

Bit Purpose/Connection
0 TIMER1/3 - [AUX:3]
1 PWM0 - [AUX:2]
2 PWM1 - [AUX:4]

Port D

Bit Purpose/Connection
0 [SPI1:!SE]
1 [SPI2:!SE]
2 [SPI3:!SE]
3 [SPI4:!SE]
7 SPI2 !SS - [SPIM:!SS]

Port E

Bit Purpose/Connection
0 [DIG1:D1]
1 [DIG1:D2]
2 [DIG1:D3]
3 [DIG1:D4]
4 [DIG1:D5]
5 [DIG1:D6]
6 [DIG1:D7]
7 [DIG1:D8]

Port F

Bit Purpose/Connection
0 AN5 - [AD1:A2]
1 AN6 - [AD1:A3]
2 AN7 - [AD1:A4]
3 AN8 - [AD1:A5]
4 AN9 - [AD1:A6]
5 AN10 - [AD2:A1]
6 AN11 - [AD2:A2]
7 [BTNS:2]

Port G

Bit Purpose/Connection
3 [BTNS:5]
4 [BTNS:3]
5 [BTNS:1]
6 [BTNS:0]
7 [BTNS:4]

Port H

Bit Purpose/Connection
0 [AD1:D1]
1 [AD1:D2]
2 [AD2:D1]
3 [AD2:D2]
4 AN12 - [AD2:A3]
5 AN13 - [AD2:A4]
6 AN14 - [AD2:A5]
7 AN15 - [AD2:A6]

Port J

Bit Purpose/Connection
0 [DIG2:D1]
1 [DIG2:D2]
2 [DIG2:D3]
3 [DIG2:D4]
4 [DIG2:D5]
5 [DIG2:D6]
6 [DIG2:D7]
7 [DIG2:D8]
Updated on 2010-05-11 08:37:41 +0000 | Requested on 2022-12-02 15:35:40 +0000